A non-volatile memory device, a representative example of which is a flash memory, has a characteristic capable of retaining stored data even when a power supply is removed. Particularly, due to recent developments in semiconductor process technology, design rules are continuously becoming narrower, and storage capacities are increasing.
Due to this increasing capacity, flash memories are being widely used as storage memories in mobile devices, digital cameras, etc., and at the time of filing of this specification, mass production of 32 Gbit products with a scale of about 30 nm is being predicted. The scale is also predicted to decrease to between 10 nm and 20 nm due to processing technology of floating gates, which are elements storing electric charges in flash memories. Various efforts in search of structures other than a two-dimensional planar cell structure that maximize the storage capacity are continuously being attempted. As an example, to overcome limits of integration in a two-dimensional structure, studies on three-dimensional structures are actively proceeding.
Particularly, there is less of a burden in adding a contact in a flash memory, in which an element storing data is formed in the cell transistor, than in other memory devices. Accordingly, it is easy to form a string structure connecting individual memory cells in series, and there is a merit in that the memory cell can be implemented in a vertical type. One recent example of a three-dimensional NAND flash memory structure is a BiCS (Bit Cost Scalable) structure.
FIG. 1 is a cross-sectional view illustrating a three-dimensional NAND flash memory structure according to a related art.
Referring to FIG. 1, a disclosed structure shows a conventional BiCS structure. That is, control gates 100 which are alternately stacked on a substrate (not illustrated) in a vertical direction are formed, and a charge storage region 110 and a channel layer 120 are formed in an internal space. That is, a region that passes through a center of the control gates 100 consists of a blocking insulating layer 115, a charge trap layer 113 and a tunneling insulating layer 111 for storing electric charges. An internal space in contact with the tunneling insulating layer 111 is filled with the channel layer 120 formed of a polycrystalline silicon material, and a gap between the control gates 100 is filled with an insulating material 130.
In the above-described structure, the charge storage region 110 usually has an ONO structure. That is, an oxide-nitride-oxide stacked structure forms the tunneling insulating layer 111—the charge trap layer 113—the blocking insulating layer 115. The ONO structure should be set to have a thickness of 10 nm to 20 nm in an actual manufacturing process. A polycrystalline silicon layer in contact with the ONO structure should be filled in the structure having a high aspect ratio. Particularly, when a conventional deposition process such as CVD or ALD is used for the ONO structure, it is difficult to form a uniform thickness in a hole passing through the control gates 100. That is, because a depth to which a deposited material should penetrate is great, a thickness of the ONO tends to be smaller at lower portions and relatively increase toward upper portions.
When the thickness of the ONO is not constant in the hole passing through the control gates 100, there is a problem in that the channel layer 120 including the polycrystalline silicon material which ultimately fills the internal space is not formed easily. Also, because of a high aspect ratio, there is a limit to adding a plurality of cell transistors to the string structure.
The above-described problem is due to a unique structure of the charge storage region 110. That is, since the charge storage region 110 has the ONO structure, a plurality of heterogeneous films are stacked. Therefore, at least two deposition processes are performed in order to form the charge storage region 110. The repetition of deposition processes causes problems such as a reduction in uniformity of heterogeneous films, and a reduction in uniformity of a threshold voltage among cell transistors in one string.